In general, performance and efficiency of a LSI depends on performance and efficiency, including power consumption, of transistors. When the threshold voltage “Vt” of transistors increases, leak current would be reduced and power consumption would improve. However, performance, including the operation speed, would be decreased, under a condition of constant voltage supply. On the other hand, when the threshold voltage “Vt” of transistors decreases, performance, including the operation speed, would be increased, however, leak current would be increased. For that reason, it is required to determine a threshold voltage “Vt” of transistors in consideration of the application of the LSI. However, since performance of a transistor depends on physical characteristics, including device structure and impurity profile, it is difficult to improve performance of a conventional bulk-CMOS.
A SOI (Silicon On Insulator) structure is based on a relatively new process technology, and has been proposed to improve performance of a transistor. In a conventional bulk-CMOS, transistors are formed on a silicon substrate. On the other hand, according to a CMOS using a SOI substrate, transistors are formed on a silicon layer, formed on an insulating layer (SiO2). According to such a CMOS using a SOI substrate, adjacent elements are completely isolated from each other, so that electrical interference including leak current and noises could be prevented. In other words, according to such a CMOS, parasitic capacitance is reduced, leak current is reduced, and electrical interferences among transistors is reduced.
When fabricating a CMOS, using a SOI substrate, a silicon layer is formed on an insulating layer and a gate is formed on the silicon layer. A PD (Partially Depleted) SOI and a FD (Fully Depleted) SOI can be distinguishably formed by adjusting a thickness of the silicon layer. Since the thicknesses of silicon layers (SOI layers) are different from each other between PD-SOI and FD-SOI, operation characteristics are different from each other. In qualification, a FD-SOI has better performance as a transistor. However, a special fabrication process is required to form a FD-SOI. On the other hand, a PD-SOI has characteristics which are similar to a bulk type.
FIG. 1 shows characteristics of a bulk-CMOS, FDSOI-CMOS and a PDSOI-COMS. In general, a FDSOI-CMOS has a better switching property as compared to the other CMOSs, however, a source/drain voltage resistant is lower. Further, according to a FDSOI-CMOS, since a drain junction area is small, a depleted region is not extended around the drain region entirely. For that reason, electric field is focused at a specific small area, so that a calorific value, which is represented by “E (electric filed)*J (current density)”, is increased. As a result, devices are easily damaged or broken with heat. Here, junction capacitance is proportional to a junction area.
Since the thickness of silicon layer (SOI layer) of a PD-SOI is large, a minority carrier (electron holes for a N-channel MOSFET) generated at the substrate side in the SOI layer is accumulated, and therefore, a substrate floating effect is easily occurred. On the other hand, since the thickness of silicon layer of a FD-SOI is small, generated carrier is transferred to a source electrode, so that a substrate floating effect is hardly occurred. In addition, according to a FD-SOI, a source/drain voltage resistant is low, so that a power supply voltage may not be determined high; and is not appropriate for a protection device because of a device damage or brokenness.
Patent Publication 1 discloses a semiconductor device in which one of source and drain regions and a part of a channel region are formed above a buried oxide layer, while the other of source and drain regions and the remaining of the channel region are formed above a Si epitaxial layer, so that a junction leak current and a capacitance are reduced.
Patent Publication 2 discloses a FD-SOI MOSFET in which a short channel effect is remarkably prevented and a Kink effect is prevented (repressed), even though such a MOSFET has a SOI layer and a BOX layer having thicknesses which are the same as those for a conventional FD-SOI MOSFET. A short channel effect is generated when drain electric filed passes through a BOX layer. A p+ region is formed to extend from a boundary between at least one of n+ source region and n+ drain region and a buried oxide layer to an opposite side of a p− body region of the at least one of n+ source region and n+ drain region. The p+ region is shaped to be “L”.
As described above, Patent Publications 1 and 2 are in the same technical field as the present invention, however, the fundamental structure and operations are different from the present invention and those priori art can not be a motivation to generate the present invention.
Patent Publication 1: JP 2006-165505A
Patent Publication 2: JP 2005-150402A